View IS65WV20488EALL_8470225.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 1 rev. a 12/12 /2014 2 m x8 low voltage, ultra low power cmos static ram features ? high - speed access time: 45ns, 55ns ? cmos low power operation C 30 mw (typical) operating C 12 w (typical) cmos standby ? ttl compatible interface levels ? single power supply C 1.65v 1.9 8 v vdd (62/65wv20488eall) C 2.2 v -- 3.6v vdd (62/65wv20488ebll) ? fully static operation: no clock or refresh required ? industrial ( - 40 o c to +85 o c) and automotive ( - 40 o c to +125 o c) temperature support description the issi is62wv20488eall/bll and is65w v20488eall/bll are high - speed, 16 m bit static rams organized as 2m words by 8 bits. it is fabricated using issi 's high - performance cmos technology. this highly reliable process coupled with innovative circuit design t echniques, yields high - performance and low power consumption devices. when is high (deselected) or when cs2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory ex pansion is provided by using chip enable and output enable inputs. the active low write enable controls both writing and reading of the memory. the is62wv20488eall/bll and IS65WV20488EALL/bll are packaged in the jedec standard 48 - pin mini bga (6mm x 8mm). b lock diagram copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability ari sing out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products . integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly a ffect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user ass ume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances january 2015
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 2 rev. a 12/12 /2014 pin configuration (2m x 8 low power) 48 - pin mini bga (b) (6mm x 8mm) pin descriptions a0 - a20 address inputs chip enable 1 input cs2 chip enable 2 input output enable input write enable input i/o0 - i/o7 input/output nc no connection vdd power gnd ground
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 3 rev. a 12/12 /2014 truth table mode cs2 i/o operation vdd current not selected x h x x high - z isb1, isb 2 (power - down) x x l x high - z isb1, isb 2 output disabled h l h h high - z icc read h l h l dout icc write l l h x din icc operating range (vdd) range ambient temperature 1.65v C 1.98 v 2.2 v - 3.6v commercial 0c to +70c is62wv20488eall (55ns) is62wv20488ebll ( 45, 55ns) industrial C 40c to +85c is62wv20488eall (55ns) is62wv20488ebll ( 45, 55ns) automotive C 40c to +125c IS65WV20488EALL (55 ns) is65wv20488ebll (55ns)
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 4 rev. a 12/12 /2014 absolute maximum rat ings and operating range absolute maximum rat ings (1) symbol parameter value unit vter m terminal voltage with respect to gnd C 0.2 to + 3.9 (v dd +0. 3 v) v tbias temperature under bias C 55 to +125 ? c v dd v dd related to gnd C 0.2 to + 3 . 9 (v dd +0. 3 v) v tstg storage temperature C 65 to +150 ? c i out dc output current (low) 20 ma note s: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat ing conditions for extended periods may affect reliability. operating range (1) range device marking ambient temperature v dd (min) v dd (typ ) v dd (max) commercial is62wv 20488eall 0 ? c to +70 ? c 1.65v 1.8 v 1.98 v industrial is62wv 20488eall - 40 ? c to +85 ? c 1.65v 1.8 v 1.98 v automotive is65wv 20488eall - 40 ? c to +125 ? c 1.65v 1.8 v 1.98 v commercial is62wv 20488e b ll 0 ? c to +70 ? c 2.2 v 3. 3 v 3.6 v industrial is62wv 20488e b ll - 40 ? c to +85 ? c 2.2 v 3. 3 v 3.6 v automotive is65wv 20488e b ll - 40 ? c to +125 ? c 2.2 v 3. 3 v 3.6 v note: 1. full device ac operation assumes a 100 s ramp time from 0 to vcc(min) and 200 s wait time after vcc stabilization. pin capacitance (1) parameter symbol test condition max units input capacitance c in t a = 25 c, f = 1 mhz, v dd = v dd (typ) 10 pf dq capacitance (io0 C io7 ) c i/o 10 pf note: 1. these parameters are guaranteed by design and tested by a sample basis only. thermal characterist ics (1) parameter symbol rating units thermal resistance from junction to ambient (airflow = 1m/s) r ja 38.3 c/w thermal resistance from junction to case r jc 6.86 c/w note: 1. t hese parameters are guaranteed by design and tested by a sample basis only.
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 5 rev. a 12/12 /2014 electrical character istics is62 (5) wv 20488eall dc electrical charac teristics - i (over the o perating range ) symbol parameter test conditions min. max. unit v oh output high voltage i oh = - 0.1 ma 1.4 v v ol output low voltage i ol = 0.1 ma 0.2 v v ih ( 1 ) input high voltage 1.4 v dd + 0.2 v v il ( 1 ) input low voltage C 0.2 0.4 v i li input leakage gnd < v in < v dd C 1 1 a i lo output leakage gnd < v in < v dd , o utput disabled C 1 1 a note s: 1. v ill (min) = - 1 .0v ac (p ulse width < 10ns ) . not 100% tested. v ihh (max ) = vdd + 1 .0v ac (p ulse width < 10ns ) . not 100% tested. is62 (5) wv 20488ebll dc electrical charac teristics - i (over the operating range) symbol parameter test conditions min. max. unit v oh output high voltage 2.2 v dd < 2.7, i oh = - 0.1 ma 2.0 v 2. 7 v dd 3 . 6, i oh = - 1 . 0 ma 2.4 v v ol output low voltage 2.2 v dd < 2.7, i ol = 0.1 ma 0. 4 v 2. 7 v dd 3 . 6, i ol = 2 .1 ma 0. 4 v v ih ( 1 ) input high voltage 2.2 v dd < 2.7 1. 8 v dd + 0. 3 v 2. 7 v dd 3 . 6 2.2 v dd + 0. 3 v v il ( 1 ) input low voltage 2.2 v dd < 2.7 C 0. 3 0. 6 v 2. 7 v dd 3 . 6 C 0. 3 0. 8 v i li input leakage gnd < v in < v dd C 1 1 a i lo output leakage gnd < v in < v dd , o utput disabled C 1 1 a notes: 1. v ill (min) = - 2 .0v ac (p ulse width < 10ns ) . not 100% tested. v ihh (max) = vdd + 2 .0v ac (p ulse width < 10ns ) . not 100% tested .
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 6 rev. a 12/12 /2014 is62 (5) wv 20488eall dc electrical charac teristics - ii for power (over the operating range) symbol parameter test conditions grade typ . max. unit icc v dd dynamic operating supply current v dd =v dd (max), i out =0ma, f=f max com. 6 1 2 ma ind. - 1 2 auto. - 12 icc1 v dd static operating supply current v dd =v dd (max), i out = 0ma, f=0hz com. 3 6 ma ind. - 6 auto. - 6 isb1 cmos standby current (cmos inputs) v dd =v dd (max), (1) 0v cs2 0.2v or (2) v dd - 0.2v, cs2 v dd - 0.2v com. 30 50 a ind. - 65 a auto. - 1 65 a note : typical values are included for reference only and are not guaranteed or tested. typical values are mea sured at vdd = vdd(typ), ta = 25 ? c is62 (5) wv 20488ebll dc electrical charac teristics - ii for power (over the operating range) symbol parameter test conditions grade typ. max. unit icc v dd dynamic operating supply current v dd =v dd (max), i out =0ma, f=f max com. 6 1 2 ma ind. - 1 2 auto. - 12 icc1 v dd static operating supply current v dd =v dd (max), i out = 0ma, f=0hz com. 3 6 ma ind. - 6 auto. - 6 isb1 cmos standby current (cmos inputs) v dd =v dd (max), (1) 0v cs2 0.2v or (2) v dd - 0.2v, cs2 v dd - 0.2v com. 30 5 0 a ind. - 6 5 a auto. - 1 65 a note : typical values are included for reference only and are not guaranteed or tested. typical values are measured at vdd = vdd(typ ), ta = 25
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 7 rev. a 12/12 /2014 ac characteristics ( 6) (over operating rang e) read cycle ac characteristics parameter symbol 4 5ns 55ns unit notes min max min max read cycle time trc 4 5 - 55 - ns 1,5 address access time taa - 4 5 - 55 ns 1 output hold time toha 8 - 8 - ns 1 , cs2 access time tacs1/tacs2 - 4 5 - 55 ns 1 access time tdoe - 2 2 - 25 ns 1 to high - z output thzoe - 18 - 18 ns 2 to low - z output tlzoe 5 - 5 - ns 2 , cs2 to high - z output thzcs/ /thzcs2 - 18 - 18 ns 2 , cs2 to low - z output tlzcs /tlzcs2 10 - 10 - ns 2 write cycle ac characteristics parameter symbol 4 5ns 55ns unit notes min max min max write cycle time twc 4 5 - 55 - ns 1,3,5 ,cs2 to write end tscs1/tscs2 35 - 40 - ns 1,3 address setup time to write end taw 35 - 40 - ns 1,3 address hold from write end tha 0 - 0 - ns 1,3 address setup time tsa 0 - 0 - ns 1,3 pulse width tpwe 35 - 40 - ns 1,3,4 data setup to write end tsd 28 - 28 - ns 1,3 data hold from write end thd 0 - 0 - ns 1,3 low to high - z output thzw e - 18 - 18 ns 2,3 high to low - z output tlzwe 10 - 10 - ns 2,3 notes: 1. tested with the load in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady - state voltage. thzoe, thzcs, thzb, and thzwe transitions are measured when the output enters a high impedance state. not 100% tested. 3. the internal write time is defined by the ov erlap of =low, cs2=high, ( or )=low, and =low. all four conditions must be in valid states to initiate a write, but any condition can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. tpwe > thzwe + tsd when oe is low. 5. address inputs must meet v ih and v il spe c during this period. any glitch or unknown inputs are not permitted. unknown input with standby mode is acceptable. 6. data retention characteristics are defined later in data retention characteristics.
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 8 rev. a 12/12 /2014 ac test conditions ( over the operating r ange) parameter symbol conditions units input rise time t r 1.0 v/ns input fall time t f 1.0 v/ns output timing reference level v ref ? v tm v output load conditions refer to figure 1 and 2 output load conditio ns figures figure1 figure2 parameters v dd =1.65~1.98v v dd =2.2~2.7v v dd =2.7~3.6v r1 13500 ? 16667? 1103 ? r2 10800 ? 15385? 1554 ? v tm vdd vdd vdd 30pf, including jig and scope r2 r1 v tm output 5pf, including jig and scope r2 r1 v tm output
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 9 rev. a 12/12 /2014 timing diagram read cycle no. 1 (1,2) (address controlled) ( = =v il , cs2= =v i h ) read cycle no. 2 (1 , 3) ( , cs2, and controlled) notes: 1. is high for a read cycle. 2. the device is continuously selected. , = vil. cs2= =v ih . 3. address is valid prior to or coincident with low and cs2 high transition. trc address i/o0 - 15 taa toha toha data valid previous data valid low - z low - z
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 10 rev. a 12/12 /2014 write cycle no. 1 ( controlled, = high or low) notes: 1. thzwe is based on the assumption when tsa=0ns after read operation. actual dout for thzwe may not appear if goes high before write cycle. thzoe is the time dout goes to high - z after goes high. 2. during this period the i/os are in output state. do not apply input signals . write cycle no. 2 ( controlled: is high during write cycle) notes: 1. thzwe is based on the assumption when tsa=0ns after read operation. actual dout for thzwe may not appear if goes high before write cycle. thzoe is the time dout goes to high - z after goes high. 2. during this period the i/os are in output state. do not apply input signals.
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 11 rev. a 12/12 /2014 write cycle no. 3 ( controlled: is low during write cycle) notes: if is low during write cycle, thzwe must be met in the application. do not apply input signal during this period. data output fr om the previous read operation will drive io bus.
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 12 rev. a 12/12 /2014 data retention characteristics symbol parameter test condition option min. typ. (2) max. unit v dr v dd for data retention see data retention waveform is62 (5) wv 20488eall 1. 5 - v is62 (5) wv 20488ebll 1 .5 - v i dr data retention current v dd = v dr (min) , (1) 0v cs2 0.2v, or (2) v dd C 0.2v, cs2 v dd - 0.2v com. - - 50 ua ind. - - 65 auto - - 1 65 t sdr data retention setup time see data retention waveform 0 - - ns t rdr recovery time see data retention waveform trc - - ns note: 1. if >vdd C 0.2v, all other inputs including cs2 must meet this condition. 2. typical values are measured at v dd =v dr(min) , t a = 25 and not 100% tested. data retention wavef orm ( controlled) data retention wavef orm (cs2 controlled) data retention mode t rdr t sdr v dd gnd v dr cs1 > v dd - 0.2v data retention mode t rdr t sdr v dd gnd v dr cs2 cs2 < 0.2v
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 13 rev. a 12/12 /2014 ordering information : is62 wv20488eall 1.65v - 1.98 v industrial r ange ( - 40 ? ? speed (ns) order part no package 55 is62 wv 20488eall - 5 5bi 48 - pin mini bga (6mmx8mm) is62 wv20488eall - 5 5bli 48 - pin mini bga (6mmx8mm), lead - free ordering information : is62 wv20488ebll 2.2 v - 3.6 v industrial r ange ( - 40 ? ? speed (ns) order part no package 45 is62 wv20488ebll - 45bi 48 - pin mini bga (6mmx8mm) is62 wv20488ebll - 45bli 48 - pin mini bga (6mmx8mm), lead - free 55 is62 wv20488ebll - 5 5bi 48 - pin mini bga (6mmx8mm) is62 wv20488ebll - 5 5bli 48 - pin mini bga (6mmx8mm), lead - free ordering information : is65wv20488ebll 2.2 v - 3.6 v automotive r ange ( - 40 ? ? speed (ns) order part no package 55 is65wv20488ebll - 5 5b a3 48 - pin mini bga (6mmx8mm) is65wv20488ebll - 5 5bl a3 48 - pin mini bga (6mmx8mm), lead - free
is62/65wv20488e all is62/65wv20488e bll integrated silicon solution, inc. - www.issi.com 14 rev. a 12/12 /2014

▲Up To Search▲

Price & Availability of IS65WV20488EALL

	To Download IS65WV20488EALL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .